Abstract:

The enhanced configuration devices are divided into two major blocks, the controller and the flash memory. Because of its large flash memory size and decompression feature, enhanced configuration devices hold configuration data for one or multiple Altera FPGAs. In addition, unused portions of the flash can be used as memory storage for a programmable logic device (PLD) or processor (e.g., Nios® processor). After onfiguration, access to the flash memory is through the external flash interface of the enhanced configuration devices. Fast passive parallel (FPP) configuration, where configuration data is sent byte-wide on the DATA[7.0] pins every clock cycle, is also supported for fast configuration times. FPP configuration is supported in Stratix series, and APEX II devices.