Abstract:

The CY7C1517V18, CY7C1528V18, CY7C1519V18 and CY7C1521V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II (Double Data Rate) architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with four 8-bit words in the case of CY7C1517V18 and four 9-bit words in the case of CY7C1528V18 that burst sequentially into or out of the device. The burst counter always starts with "00" internally in the case of CY7C1517V18 and CY7C1528V18. On CY7C1519V18 and CY7C1521V18, the burst counter takes in the last two significant bits of the external address and bursts four 18-bit words in the case of CY7C1519V18, and four 36-bit wo