Part Number: CY7C09189/99
File Name: cy7c09199_8.pdf
No. of Pages: 19
File Size: 335.75 KB
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Abstract:
The CY7C09089/99 and CY7C09189/99 are high-speed syn-chronous CMOS 64K and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. [4] Reg- isters on control, address, and data lines allow for minimal set- up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 15 ns after the address is clocked into the device. Pipelined output or flow- through mode is selected via the FT/Pipe pin.
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