Part Number: CF51004-2
File Name: cfg_cf51003.pdf
No. of Pages: 68
File Size: 481.69 KB
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Abstract:
"APEX II devices can be configured using the passive serial (PS), fast passive parallel (FPP), passive parallel asynchronous (PPA), and Joint Test Action Group (JTAG) configuration schemes. The configuration scheme used is selected by driving the APEX II device MSEL1 and MSEL0 pins either high or low as shown in Table 6–1. If your application only requires a single configuration mode, the MSEL pins can be connected to VCC (VCCIO of the I/O bank where the MSEL pin resides) or to ground. If your application requires more than one configuration mode, you can switch the MSEL pins after the FPGA is configured successfully. Toggling these pins during user-mode does not affect the device operation; however, the MSEL pins must be valid before a reconfiguration is initiated. "
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