Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will http://onsemi.com accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or MARKING DIAGRAM* 2.5 Gb/s, respectively. As such, the NB6N11S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution 16 1 applications. The NB6N11S has a wide input common

The VHC240 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC240 is an inverting 3-STATE buffer having two active-LOW output enables. This device is designed to drive buslines or buffer memory address registers.

This document explains how an IN endpoint in the ISP1582, ISP1583 and the ISP1761Peripheral Controller can be cleared.When the Universal Serial Bus (USB) connector is pulled out during a data transfer, there may still be residual data in the IN endpoint buffer in use. This can cause data corruption when the next data transaction is scheduled. To avoid this, clear the IN endpoint buffer properly. A soft reset or a bus reset cannot properly clear the IN endpoint because the endpoint is like a stat

This 25-bit 1:1 / 14-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. In the 1:1 pinout configuration, only one device per DIMM is requred to drive nine SDRAM loads. In the 1:2 pinoutconfiguration, two devices per DIMM are required to drive eighteen SDRAM loads. All inputs are SSTL_18, except reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specification

TC4049B, TC4050B contain six circuits of buffers. TC4049B is nverter type and TC4050B is non-inverter type. Since one TTL or DTL can be directly driven having large output current, these are useful for interfacing from CMOS to TTL or DTL. As voltage up to VSS + 18 volts can be applied to the nput regardless of VDD, these can be also used as the level converter IC's which converts CMOS logical circuits of 15 volts or 10 volts system to CMOS/TTL logical circuits of 5 volts system. Ideal switc

Description The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device http://onsemi.com features fully differential clock paths to minimize both device and system skew. The LVE310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated i

A zero delay buffer is a device that can fan out one clock signal into multiple clock signals, with zero delay and very low skew between the outputs. This device is well-suited for a variety of clock distribution applications requiring tight input-output and output-output skews. A simplified diagram of a zero delay buffer is shown in figure 1. A zero delay buffer is built with a PLL that uses a reference input and a feedback input. The feedback input is driven by one of the outputs. The pha

The ACQ241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. The ACQ utilizes Fairchild FACT Quiet Series™ technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance.

The IS657B is an optically integrated circuit detector with schmitt trigger open collector buffer output. It is mounted in a clear plastic lateral side looking package which enables these devices to display superior mechanical resolutions, coupled characteristics and reliability in a low cost housing.

BCSA2S1S2S3S4S5S6> x< x> x< xx = 0100 %SA1S1S2S3> 3.3V Octal buffer/line driver with 30 <font face="symbol">&#87;</font> series termination resistors; 3-State, 74LVT2241,74LVT2241D 74LVT2241D 74LVT2241DB 74LVT2241DB 74LVT2241PW 74LVT2241PW 74LVT2241PW 74LVT2241PW