The CoolRunner™ XPLA3 XCR3512XL device is a 3.3V,512 macrocell CPLD targeted at power sensitive designsthat require leading edge programmable logic solutions. Atotal of 32 function blocks provide 12,000 usable gates.Pin-to-pin propagation delays are as fast as 7.0 ns with amaximum system frequency of 135 MHz.

The CY3LV512/010 (high-density CY3LV Series) CPLD boot EEPROMs provide an easy-to-use, cost-effective configura- tion memory for Complex Programmable Logic Devices. The CY3LV Series is packaged in the popular 20-pin PLCC. These devices support a system-friendly READY pin, which signifies a "good" power level to the CPLD and can be used to ensure reliable system power-up. The CY3LV Series boot PROMs can be programmed with in- dustry-standard programmers or Cypress's CYDH2200E CPLD b

The XC95288XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6,400 usable gates withpropagation delays of 6 ns.

WarpISR is a complete ISR CPLD design and programming solution. It includes Warp software and the Delta39K Ultra37000 ISR Programming Kit. Warp is a state-of-the-art HDL compiler for designing with Cypress's Complex Program- mable Logic Devices (CPLDs). For a complete description of Warp, please see the CY3120 data sheet. For a complete description of the ISR PC programmer, please see the CY3900i Delta39KUltra37000 ISR Programming Kit data sheet.

The ATF1502AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel's proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1502AS's enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.

Key features of the CoolRunner-II CPLD family include DualEDGE triggered registers, a global clock divider, and voltage referenced I/O standards including SSTL_2. These features provide the capability to interface a CoolRunner-II CPLD with high speed memory devices such as DDR SDRAM.

The I2C bus is a popular serial, two-wire interface used in many systems because of its low overhead. The two-wire interface minimizes interconnections so ICs have fewer pins, and the number of traces required on printed circuit boards is reduced. Capable of 100 KHz operation, each device connected to the bus is software addressable by a unique address with a simple Master/Slave protocol.

The CoolRunner™-II 32-macrocell device is designed forboth high performance and low power applications. Thislends power savings to high-end communication equipmentand high speed to battery operated devices. Due to the lowpower stand-by and dynamic operation, overall system reliabilityis improved

The goal of this application note is to discuss XC9500XL CPLD power estimation and optimization and provide the reader with an understanding of sense-amplifier based CPLD power dissipation. A brief discussion of the process for estimation is given. With this information, you can accurately assess the power dissipation for a design. You will also be given guidelines permitting you to make key choices to manage the power dissipation of your design and understand the package thermal limits.

The XC95288 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 6,400 usable gates with propagation delays of 15 ns. See Figure 2 for the architecture overview.