The GS81302T08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302T08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burstSRAMs with No Bus Latency (NoBL) logic, respectively. They are designed to support unlimited true back-to-backRead/Write operations with no wait states. TheCY7C1460AV33/CY7C1462AV33/CY7C1464AV33 areequipped with the advanced (NoBL) logic required to enableconsecutive Read/Write operations with data being trans-ferred on every clock cycle. This feature dramatically improvesthe throughput of da

The uPSD325x Series combines a fast 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix including USB, to form an ideal embedded controller. At its core is an industry-standard 8032MCU operating up to 40MHz.

The GS864218/36/72 is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Organized as 512K words by 16 bits, Fast Cycle Time : 55ns, 70ns, Standby Current : 100uA, Deep power-down Current : 10uA (Memory cell data invalid), Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15), Compatible with low power SRAM, Single Power Supply Voltage : 3.0V±0.3V, Package Type : 48-ball FBGA, 6x8mm.

The ?PD44165082 is a 2,097,152-word by 8-bit, the ?PD44165182 is a 1,048,576-word by 18-bit and the ?PD44165362 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.The ?PD44165082, ?PD44165182 and ?PD44165362 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These produ

The FullFlex™ Dual-Port SRAM families consist of 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two ports are provided, allowing the array to be accessed simulta- neously. Simultaneous access to a location triggers determin- istic access control. For FullFlex72, these ports can operate independently in DDR mode with 36-bit bus widths or in SDR mode with 72-bit bus widths. For FullFlex36 and FullFlex18, the po

The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega- bit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.

The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. E

features of the QDRII architecture is the echo-clock (CQ) output, which is frequency locked to the device input clock (K) but edge aligned to the data transmitted on the Read path outputs (Q). The CQ clock output is re-timed to align with the Q data outputs using a delay-locked loop (DLL) circuit internal to the QDRII memory device. This clock forwarding, or source-synchronous, interface method allows greater timing margin for the read data capture operation at the far-end device.Figure1, page3