DescriptionFX-402 Phase Detector & LDLD (7)Figure 1. Functional block diagramFIN(13)(8) FOUT1VCC(14)VMON(5)(6)(3, 12) Controller(9) CFOUT1(10) FOUT2(11)CFOUT2SEL0 (1)SEL1 (2)FIN1FIN2FIN4FIN31. See Standard Frequencies and Ordering Information.2. Parameters are tested with production test circuit below (Fig 2).3. Parameters are tested at ambient temperature with test limits guard banded for speci ed operating temperature.4. Measured from 20% to 80% of a full output swing (Fig 3).5. Not tested

Features · Wide VCCA and VCCB Operating Range: 0.9 V to 4.5 V 1 VCM · High-Speed w/ Balanced Propagation Delay UDFN8 G · Inputs and Outputs have OVT Protection to 4.5 V MU SUFFIX CASE 517AJ · Non-preferential VCCA and VCCB Sequencing · Outputs at 3-State until Active VCC is Reached VC = Specific Device Code · Power-Off Protection M = Date Code G = Pb-Free Package · Outputs Switch to 3-State with VCCB at GND · Ultra-Small Packaging: 1.8 mm x

1 A Output Rating Internal Sequencer for Full or Half-Step Operation PWM Constant-Current Motor Drive Cost-Effective, Multi-Chip Solution 100 V, Avalanche-Rated NMOS Low rDS(on) NMOS Outputs (700 m. typical) Advanced, Improved Body Diodes

Basic voltage level translator utilizes a voltage comparator to translate an input voltage range into an output voltage range. First step is to determine the input voltage range, which involves an input low voltage level VIN(low) and an input high voltage level, VIN(high). Next step is to figure out the proper reference voltage level, at VREF. In many cases VREF can be simply midpoint between VIN(low) and VIN(high). In other cases, one may want to skew the VREF voltage level towards either VIN(l

DescriptionThe part is supplied in an eight leadpackage, the SM8, (see Appendix B) andrequires only four connections into thecircuit and four external resistors toeffect a complete, accurate and costeffective current sense plus leveltranslation circuit. The maximumoperating ratings of the part are 30V and1A, though in practice the operatingcurrent is likely to be of the order of afew mA at most.The part is connected into the circuitusing the E1, E2, E3 and E4 pins,corresponding to the Emitter no

The SY89321L is a differential LVPECL-to-LVTTL translator requiring only a single +3.3V power. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The SY89321L is functionally equivalent to the SY100EPT21L, but in an ultra-small 8-lead MLF® package that features a 70% smaller footprint.

The PLL130-08 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.0GHz.

DongleComputerNotebookDocking StationGPUSN75DP139T SLLS977

Description The MC100EP91 is a triple any level positive input to NECL output MARKING DIAGRAMS* translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, 20 CML or LVDS signals, and translates them to differential NECL 20 output signals (-3.0 V / -5.5 V). MC100EP91 To accomplish the level translation the EP91 requires three power 1 AWLYYWWG rails. The VCC pins should be connected to the positive power supply, SO-20 WB and the VEE pin should be connected to the negative power supply. DW SUFFIX

The SY89834U is a high-speed, 1GHz LVTTL/CMOS-to-LVPECL fanout buffer/translator optimized for high-speed ultra-low skew applications. The input stage is designed to accept two single-ended LVTTL/CMOS compatible signals that feed into a 2:1 MUX.