Do not drive signals into these pins. Exceptions are the configuration pins and the pins noted in this pin list. These pins should be properly connected on the board when prototyping with the Stratix II FPGA device. Make sure to check the pin out information for the Stratix II FPGA prototype compiled design when laying out the board to ensure compatibility between the HardCopy II device and the Stratix II FPGA prototype device.

Program and reprogram devices after they are soldered onto the printed circuit board (PCB), minimizing the possibility of lead damage or electrostatic discharge (ESD) exposure. Manufacture systems before you finalize device configuration. Perform boundary-scan test (BST) procedures and program devicesusing in-circuit testers. Upgrade systems in the field after they have been shipped.

EPM3064A Dedicated Pin-Outs ver. 1.0 Dedicated Pin 44-Pin PLCC 44-Pin TQFP 100-Pin TQFP INPUT/GCLK1 43 37 87 INPUT/GCLRn 1 39 89 INPUT/OE1 44 38 88 INPUT/OE2/GCLK2 2 40 90 TDI (1) 7 1 4 TMS (1) 13 7 15 TCK (1) 32 26 62 TDO (1) 38 32 73 GNDINT 22, 42 16, 36 38, 86 GNDIO 10, 17, 30, 36 4, 11, 24, 30 11, 26, 33, 43, 53, 59, 65, 74, 78, 95 VCCINT (3.3 V Only) 3, 23 17, 41 39, 91 VCCIO (2.5 V or 3.3 V) 15, 35 9, 29 3, 18, 34, 51, 66, 82 No Connect (N.C.) ­ ­ 1, 2, 5, 7, 22, 24, 27, 28, 49, 5"

Synchronous static RAM (SRAM) architectures support the high throughput requirements of communications, networking, and digital signal processing (DSP) systems. The successor to quad data rate (QDR) SRAM, QDRII and QDRII+ SRAM support higher memory bandwidth and improved timing margins and offer more flexibility in system designs. The QDRII+ SRAM is the latest addition to the quad data rate SRAM family.

Tables 12"1 through 12"3 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for 1.5-V HardCopy® Stratix® devices.

The hot-socketing feature lessens the board design difficulty when using Cyclone II devices on printed circuit boards (PCBs) that also contain a mixture of 3.3-, 2.5-, 1.8-, and 1.5-V devices. With the Cyclone II hot-socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board.

The worldwide interoperability for microwave access (WiMAX) standard is an emerging technology with significant potential that is poised to revolutionize the broadband wireless internet access market. The diverse hardware requirements for these systems including processing speed, flexibility, integration and time-to-market necessitate an FPGA based implementation platform.

This document addresses known errata and documentation issues for the Altera® RapidIO MegaCore® function version 3.0.1. Errata are functional defects or errors, which may cause the RapidIO MegaCore function to deviate from published specifications. Documentation issues include errors, unclear descriptions, or omissions from current published specifications or product documents.

Stratix III devices use SRAM cells to store configuration data. As SRAM memory is volatile, you must download configuration data to the Stratix III device each time the device powers up. You can configure Stratix III devices using one of four configuration schemes:

This document addresses known errata and documentation issues for the UTOPIA Level 2 Master MegaCore® function v7.0. Errata are functional defects or errors, which may cause the UTOPIA Level 2 Master MegaCore function to deviate from published specifications. Documentation issues include errors, unclear descriptions, or omissions from current published specifications or product documents.