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SLUU185A

Features ...2 1.2 Kit Contents...2 1.3 Ordering Information ...3 2 Installation and Setup...3 2.1 Minimum System Requirements ...3 2.2 Final Test Board Specifications...3 2.3 Interface Connections ...3 2.3.1 Test Head Fixture Interface ...4 2.3.2 Computer to Test System Interface...4 2.4 System Power Up...4 3 Software Contents and Installation ...5 3.1 Software Contents...5 3.2 Software Installation ...5 4 Operation ...5 4.1 Starting the Program ...6 4.2 Initialization...6 4.2.1 Load EEPROM ...6

Relevant Keywords: 
SLUU185A

SRC4192IDBG4, SRC4293, SRC4193I, SRC4192IDB, SRC4193IDBRG4, SRC4193, SRC4192I, SRC4193IDBR, SRC4192IDBRG4, SRC4192, SRC4193IDBG4, SRC4192IDBR, SRC4193IDB

DESCRIPTION Supports I2S, Left Justified, Right Justified, and The SRC4192 and SRC4193 are asynchronous sample rate TDM Data Formats converters designed for professional and broadcast audio Supports 16, 18, 20, or 24-Bit Audio Data applications. The SRC4192 and SRC4193 combine a wide TDM Mode allows daisy chaining of up to eight input-to-output sampling ratio with outstanding dynamic range devices and ultra low distortion. Input and output serial ports support q SUPPORTS 24-, 20-, 18-, or 16-BIT

Relevant Keywords: 
SRC4192IDBR, SRC4193IDB, SRC4192IDBG4, SRC4293, SRC4193I, SRC4192IDB, SRC4193IDBRG4, SRC4193, SRC4192I, SRC4193IDBR, SRC4192IDBRG4, SRC4192, SRC4193IDBG4

MSP50C605MIXED-SIGNAL PROCESSORSPSS025B FEBRUARY 2

descriptionThe MSP50C605 is a low-cost, mixed-signal processor that combines a speech synthesizer, general-purposeI/O, onboard ROM, and direct speaker drive in a single package. The computational unit utilizes a powerful newDSP which gives the MSP50C605 unprecedented speed and computational flexibility compared with previousdevices of its type. The MSP50C605 supports a variety of speech and audio coding algorithms, providing arange of options with respect to speech duration and sound quality.The

Relevant Keywords: 
MAX18,85, PD799, V01V, MSP50C605MIXED-SIGNAL, PROCESSORSPSS025B, V2mAI, I/O(1, PD4D, TYP070,130,650,10NOTESA.All, MSP50C605, PF716, V2550mVR, FLATPACK4040022/B, PD421/F, SS17, MS-022IMPORTANT, PF0PF721/F, V23V, 25C,10, PC789, ROM0x0800, MHz15mAI, PE746, V10mAI, 25C,1, MSP50C614, RAM32, V5mAI

HCT390, CD74HC390EE4, CD74HC390MTG4, CD74HCT390MG4, CD74HC390M96G4, CD74HCT390M, HCT39, CD74HC390E, CD74HC390MTE4, CD74HCT390ME4, CD74HC390M96E4, CD74HCT390EE4, CD74HCT390MTG4, CD74HC390, CD74HC390MT, CD74HCT390M96G4, CD74HC390M96, CD74HCT390E, CD74HCT390

Description · Two BCD Decade or Bi-Quinary Counters The CD74HC390 and 'HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are [ /Title · One Package Can Be Configured to Divide-by-2, 4, pin compatible with low-power Schottky TTL (LSTTL). These 5,10, 20, 25, 50 or 100 (CD74 devices are divided into four separately clocked sections. HC390 · Two Master Reset Inputs to Clear Each Decade The counters have two divide-by-2 sections and two div

Relevant Keywords: 
CD74HC390M, CD74HCT390, CD74HCT390MT, CD74HC390ME4, CD74HCT390M96, HCT390, CD74HC390EE4, CD74HC390MTG4, CD74HCT390MG4, CD74HC390M96G4, CD74HCT390M, HCT39, CD74HC390E, CD74HC390MTE4, CD74HCT390ME4, CD74HC390M96E4, CD74HCT390EE4, CD74HCT390MTG4, CD74HC390, CD74HC390MT, CD74HCT390M96G4, CD74HC390M96, CD74HCT390E, CD74HCT390MTE4, CD74, CD74HC390MG4, CD74HCT390M96E4

SLAU051

Description Chapter 2 ­ Modes of Operation Appendix A ­TLV320AIC27 Register Block Diagram Appendix B ­DSP Interface Appendix C ­Audio Control Block Diagram Appendix D ­EVM Shared Clock Configuration Appendix E ­Serial Interface Register Map Appendix F ­Software Drivers Appendix G ­PC Board and Bill of Materials Appendix H ­Schematics Trademarks All trademarks are the property of their respective owners. Read This First iii Running Title--Attribute Reference Co

Relevant Keywords: 
SLAU051

SPNU128A, SPNU028, SPNU022, SPNU010

descriptions, the instruction or command is in a bold face font, and parameters are in italics. Portions of a syntax that are in bold face should be entered as shown; portions of a syntax that are in italics describe the kind of information that should be entered. Here is an exam- ple of a command syntax: prog address, length [, filename] prog is the command. This command has three parameters, indicated by address, length, and filename. The third parameter is optional. - Square brackets ( [ and

Relevant Keywords: 
SPNU128A, SPNU028, SPNU022, SPNU010

PCM1774RGPRG4, PCM1774RGPR, PCM1774RGP, PCM1774RGPTG4, PCM1774, PCM1774RGPT

DESCRIPTION · Sampling Frequency: 5 kHz to 50 kHz The PCM1774 is a low-power stereo DAC designed · Operation From a Single Clock Input Without for portable digital audio applications. The device PLL integrates headphone amplifier, line amplifier, line · System Clock: input, boost amplifier, programmable gain control, ­ Common-Audio Clock (256 fS/384 fS), 12/24, analog mixing, and sound effects. It is available in a 13/26, 13.5/27, 19.2/38.4, 19.68/39.36 MHz small-footpri

Relevant Keywords: 
PCM1774RGPT, PCM1774RGPRG4, PCM1774RGPR, PCM1774RGP, PCM1774RGPTG4, PCM1774

SN74ACT7804, SN74ACT7804-25DLR, ACT7804-40, SN74ACT7814, SN74ACT7804-25DL, ACT7804-25, SN74ACT7806, SN74ACT7804-20DLR, ACT7804-20, SN74ACT7804-40DLR, SN74ACT7804-20DL, SN74ACT7804-40DL

description D1 20 37 Q3 D0 21 36 Q2 A FIFO memory is a storage device that allows HF 22 35 GND data to be written into and read from its array at PEN 23

Relevant Keywords: 
SN74ACT7804-20DL, SN74ACT7804-40DL, SN74ACT7804, SN74ACT7804-25DLR, ACT7804-40, SN74ACT7814, SN74ACT7804-25DL, ACT7804-25, SN74ACT7806, SN74ACT7804-20DLR, ACT7804-20, SN74ACT7804-40DLR

TPA3100D2PHPG4, TPA3100D2RGZR-P, TPA3100D2PHP, TPA3100D2RGZR, TPA3100D2EVM, TPA3100D2RGZTG4, TPA3100D2PHPRG4, TPA3100D2, TPA3100D2RGZT, TPA3100D2PHPR, TPA3100D2RGZRG4

DESCRIPTION · Operates from 10 V to 26 V The TPA3100D2 is a 20-W (per channel) efficient, Class-D audio power amplifier for driving bridged-tied · 92% Efficient Class-D Operation Eliminates stereo speakers. The TPA3100D2 can drive stereo Need for Heat Sinks speakers as low as 4 . The high efficiency of the · Four Selectable, Fixed Gain Settings TPA3100D2, 92%, eliminates the need for an · Differential Inputs external heat sink when playing music. · Thermal and

Relevant Keywords: 
TPA3100D2PHPR, TPA3100D2RGZRG4, TPA3100D2PHPG4, TPA3100D2RGZR-P, TPA3100D2PHP, TPA3100D2RGZR, TPA3100D2EVM, TPA3100D2RGZTG4, TPA3100D2PHPRG4, TPA3100D2, TPA3100D2RGZT

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