Gangable up to 6 sections, Large range of ohmic values: 5 ? to 30 k?, Extra taps upon request.

Two-part ceramic cement/coating with excellent electrical insulating properties up to +1200°F [+650°C]. Recommended as a high-temperature cement and coating for free-filament strain gages (wire and foil) and thermocouple applications. Provides good adhesion to most metals.

The attached spice model describes the typical electrical characteristics of the p- hannel vertical DMOS. The subcircuit model is extracted and optimized over the ?55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.

Polarized aluminum electrolytic capacitors, non-solid electrolyte Axial leads, cylindrical aluminum case, insulated with a blue sleeve Mounting ring version not available in insulated form Taped versions up to case ? 15 x 30 mm available for automatic insertion Charge and discharge proof Extra long useful life: up to 8000 hours at 125 °C, high reliability Lowest ESR levels providing very high ripple current capability Extended temperature range: usable up to 150 °C Lead diameter ? d =

The MBR30.WT center tap Schottky rectifier has been optimized for very low forward voltage drop, with moderate leakage. The proprietary barrier technology allows for reliable operation up to 150° C junction temperature. Typical applications are in switching power supplies, converters, free-wheeling diodes, and reverse battery protection.

Glass passivated junction, Hermetically sealed package, Low reverse current, Soft recovery characteristics, Lead (Pb)-free component, Component in accordance to RoHS 2002/95/EC and WEEE 2002/96/EC.

Only one wire bound required, Small size: 0.015 inches square, Single top contact, Resistance range: 100 ? to 100 k?, Tolerance: ± 10 %, ± 20 %, ± 25 %, ± 50 %, Packaging: Matrix tray.

The 60048 is a high precision, stainless steel, single point platform load cell.

The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the ?55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.