DDR2, AS4DDR264M72PBG1-38, DDR2-SDRAM, AS4DDR264M72PBG1R-5, AS4DDR264M72PBG1-3, DDR2-667, AS4DDR264M72PBG1R-38, AS4DDR264M72PBG1, DDR2-533, AS4DDR264M72PBG1R-3, DDR2-400, AS4DDR264M72PBG1-5
FEATURES BENEFITS DDR2 Data rate = 667, 533, 400 61% Space Savings Available in Industrial, Enhanced and Extended Temp 55% I/O reduction vs Individual CSP approach Package: Reduced part count · Proprietary Enchanced Die Stacked iPEM Reduced trace lengths for lower parasitic · 208 Plastic Ball Grid Array (PBGA), 16 x 23mm capacitance · 1.00mm ball pitch Suitable for hi-reliability applications Differential data strobe (DQS, DQS#) per byte Upgradable to 128M x 72 density in future Internal, pipelined, double data rate architecture Pin/Function equivalent to White 4n-bit prefetch architecture W3H64M72E-xBSx DLL for alignment of DQ and DQS transitions with clock signal Eightinternal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes (I/T Version) On Die Termination (ODT) Adjustable data output drive strength 1.8V ±0.1V common core power and I/O supply Programmable CAS latency: 3, 4, 5, 6 or 7 Posted CAS addit
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Relevant Keywords:
AS4DDR264M72PBG1R-3, DDR2-400, AS4DDR264M72PBG1-5, DDR2, AS4DDR264M72PBG1-38, DDR2-SDRAM, AS4DDR264M72PBG1R-5, AS4DDR264M72PBG1-3, DDR2-667, AS4DDR264M72PBG1R-38, AS4DDR264M72PBG1, DDR2-533
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