description and is subject to change without notice. Hynix Electronics does not assume any respon- sibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Jun. 2004 1 HY5DS573222F(P) Revision History No. History Draft Date Remark 0.1 Defined Target Spec. Mar. 2004 0.2 Supports Lead free parts for each speed grade Apr. 2004 0.3 CL, AC parameter, IDD5 change Apr. 2004 0.4 CL, tCK_max, tRAS, tDAL change & Comment of DLL_off condition Jun. 2004 Rev. 0.4 / Jun. 2004 2 HY5DS573222F(P) PRELIMINARY DESCRIPTION The Hynix HY5DS573222 is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 8Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edge