description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Jul. 2005 1 HY5RS573225AFP Revision History Revision No. History Draft Date Remark 0.1 Defined target spec. Mar. 2005 0.2 Typo Corrected May. 2005 0.3 VDD/ VDDQ min/ max value change Jul. 2005 Rev. 0.3 / Jul. 2005 2 HY5RS573225AFP DESCRIPTION PRELIMINARY The Hynix HY5RS573225 is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. The Hynix HY5RS573225 is internally configured as a quad-bank DRAM. The Hynix HY5RS573225 uses a double data rate architecture to achieve high-speed opreration. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Hynix HY5RS573225 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corres