DESCRIPTION 12.3 UART queue 2.1 Compatibility between P90CL301AFH and 12.4 I2C-bus interface P90CL301BFH 12.5 Serial Control Register (SCON) 3 ORDERING INFORMATION 13 PULSE WIDTH MODULATION OUTPUTS (PWM) 4 BLOCK DIAGRAM 13.1 Prescaler PWM Register (PWMP) 5 PINNING INFORMATION 13.2 PWM Data Registers (PWM0 and PWM1) 5.1 Pinning 14 ANALOG-TO-DIGITAL CONVERTER (ADC) 5.2 Pin description 14.1 ADC Control Register (ADCON) 6 SYSTEM CONTROL 15 ON-BOARD TEST CONCEPT 6.1 Memory organization 6.2 Programmable chip-select 15.1 ONCE mode 6.3 Dynamic bus port sizing 15.2 Test ROM 6.4 System Control Register (SYSCON) 16 ON-CHIP RAM 6.5 Reset operation 17 REGISTER MAPPING 6.6 Clock generation 6.7 Interrupt controller 18 LIMITING VALUES 6.8 Power reduction modes 19 DC CHARACTERISTICS 7 CPU FUNCTIONAL DESCRIPTION 20 ADC CHARACTERISTICS 7.1 General 21 AC CHARACTERISTICS 7.2 Programming model and data organization 22 8051 BUS TIMING 7.3 Processing states and exception processing 7.4 Tracing 23 TIMING DIAGRAMS 7.5 Stack format 24