description.DescriptionThe CoolRunner-II 64-macrocell device is designed for bothhigh performance and low power applications. This lendspower savings to high-end communication equipment andhigh speed to battery operated devices. Due to the lowpower stand-by and dynamic operation, overall system reli-ability is improved.This device consists of four Function Blocks inter-connectedby a low power Advanced Interconnect Matrix (AIM). TheAIM feeds 40 true and complement inputs to each FunctionBlock. The Function Blocks consist of a 40 by 56 P-termPLA and 16 macrocells which contain numerous configura-tion bits that allow for combinational or registered modes ofoperation. Additionally, these registers can be globally reset or presetand configured as a D or T flip-flop or as a D latch. Thereare also multiple clock signals, both global and local productterm types, configured on a per macrocell basis. Output pinconfigurations include slew rate limit, bus hold, pull-up,open drain, and programmable FeaturesOptimized for 1.8V systems-As fast as 4.6 ns pin-to-pin logic delays -As low as 15 Industrys best 0.18 micron CMOS CPLD -Optimized architecture for effective logic synthesis-Multi-voltage I/O operation 1.5V to 3.3VAvailable in multiple package options-44-pin VQFP with 33 user I/Os-48-land QFN with 37 user I/Os-56-ball CP BGA with 45 user I/Os-100-pin VQFP with 64 user I/Os-Pb-free available for all packagesAdvanced system features-Fastest in system programming1.8V ISP using IEEE 1532 (JTAG) interface-IEEE1149.1 JTAG Boundary Scan Test-Optional Schmitt-trigger input (per pin)-Two separate I/O banks-Flexible clocking modesOptional DualEDGE triggered registers-Global signal options with macrocell controlMultiple global clocks with phase selection per macrocellMultiple global output enablesGlobal set/reset-Efficient control term clocks, output enables, and set/resets for each macrocell and shared across function blocks-Advanced design security-Optional bus-hold, 3-state, or weak pu Specification 20042008 Xilinx, Inc. All Xilinx