description.DescriptionThe CoolRunner-II 32-macrocell device is designed forboth high performance and low power applications. Thislends power savings to high-end communication equipmentand high speed to battery operated devices. Due to the lowpower stand-by and dynamic operation, overall system reli-ability is improved.by a low power Advanced Interconnect Matrix (AIM). TheAIM feeds 40 true and complement inputs to each FunctionBlock. The Function Blocks consist of a 40 by 56 P-termPLA and 16 macrocells which contain numerous configura-tion bits that allow for combinational or registered modes ofoperation. Additionally, these registers can be globally reset or presetand configured as a D or T flip-flop or as a D latch. Thereare also multiple clock signals, both global and local productterm types, configured on a per macrocell basis. Output pinconfigurations include slew rate limit, bus hold, pull-up,input is available on a per input pin basis. In addition to stor-ing macrocell output st FeaturesOptimized for 1.8V systems-As fast as 3.8ns pin-to-pin logic delaysA quiescent current Industrys best 0.18 micron CMOS CPLD-Optimized architecture for effective logic synthesis-Multi-voltage I/O operation: 1.5V through 3.3V Available in multiple package options-32-land QFN with 21 user I/Os-44-pin VQFP with 33 user I/Os-56-ball CP BGA with 33 user I/Os-Pb-free available for all packagesAdvanced system features-Fastest in system programming1.8V ISP using IEEE 1532 (JTAG) interface-IEEE1149.1 JTAG Boundary Scan Test-Optional Schmitt-trigger input (per pin)-RealDigital 100% CMOS product term generation-Flexible clocking modes-Optional DualEDGE triggered registers-Global signal options with macrocell controlMultiple global clocks with phase selection per macrocellMultiple global output enablesGlobal set/reset-Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks-Advanced design security-Open-drain output option for Wired-O Specification 20042008 Xilinx, Inc. All Xilinx