DescriptionThe PPC440MC DDR2 Memory Controller interfaces directly to the PowerPC processor through theMCI (see Figure1). To achieve hardware functionality and maximum performance with the memorycontroller interface, users should use the relevant optimal UCF provided in the EDK PCORE directory.There is only one optimal UCF for each device/package/processor combination.X-Ref Target - Figure 1I/O SignalsTable1 defines the PPC440MC DDR2 Memory Controller signals.Figure 1:PPC440 MCI and PPC440MC DDR2 Memory Controller Block DiagramTable 1: PPC440MC DDR2 Memory Controller I/O Signal DescriptionSignal NameInterfaceSignalTypeInitial StatusDescriptionPPC440 MCI SignalsMIMCREADNOTWRITEMCIIThis signal indicates if the operation is a read or a writeMIMCADDRESSVALIDMCIIWhen asserted, this signal indicates the data on the address bus is valide for the data on the data busMIMCWRITEDATAVALIDMCIIWhen asserted, this signal indicates the data on the data bus is validMIMCBANKCONFLICTMCIIThis signal is as FeaturesSupports a maximum performance of 333MHz in the fastest speed gradeSupports 16-bit, 32-bit, and 64-bit data widths, and 72-bit data width with ECC (DQ:DQS=8:1)DIMMs and componentsSupports the following DDR2 SDRAM features:CAS latencies (3, 4, 5)Additive latencies (0, 1, 2, 3, 4)On-die termination (ODT)Burst lengths (4, 8)Supports bank management (up to four banks open)Performs the memory device initialization sequence upon power-upPerforms auto-refresh cyclesDDR2 Memory Controller forPowerPC 440 ProcessorsDS567 (v1.1.1) March 31, 2008Reference Design FactsReference Design SpecificsSupported Device FamilyVirtex-5 FXT Platform FPGAsVersion of Reference DesignPPC440MCv1_01_aResources UsedLUTsSee Table9FFsSee Table9Block RAMsSee Table9Special FeaturesNoneProvided with Reference DesignDocumentationProduct SpecificationDesign File FormatsVerilogConstraints FileUCF in EDK PCORE directoryVerificationVerilog TestbenchInstantiation TemplateVerilog WrapperDesign Tool RequirementsXilinx Im SpecificationDesign File FormatsVerilogConstra