UG197, Virtex-5 Integrated Endpoint Block for PCI Express Designs User Guide
description in Table2-15, page42 and added a footnote tied to power state D3. Clarified request types when crossing a 4KB boundary in Table4-2, page71.Replaced Chapter3, Designing with LogiCORE IP for the Endpoint Block.Addition of Known Restrictions, page 79.RUG197 (v1.3) June 2, 2008www.xilinx.comVirtex-5 Integrated Endpoint Block User Guide06/02/081.3Updated TX Transmission Issues Due to Lack of Data Credits, page 79 including workaround. Added Lane Reversal, page 78.Fixed LLKRXDSTREQN in Invalid Cycles in LLKRXPREFERREDTYPE Signal, page 82.Updated Credit Leak When Transmitting Completion TLPs, page 87. AddedReceipt of Back-to-Back ACK DLLPs, page 88.DateVersionRevisionVirtex-5 Integrated Endpoint Block User Guidewww.xilinx.comUG197 (v1.3) June 2, 2008Virtex-5 Integrated Endpoint Block User Guidewww.xilinx.com 5UG197 (v1.3) June 2, 2008Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RVirtex-5 Integrated Endpoint Block for PCI Expres PCI Express, PCIe, endpoint, 197, v5, virtex, GTP, virtex5
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