Description The MPEG2 decoder is designed to provide high performance solutions for a broad range of motion image applications. This highly integrated application specific virtual component (ASVC) is for standard definition video, compliant with ISO/IEC 13818-2 (MPEG2) and capable of decoding video streams at the Main Profile at Main Level (MP@ML). The CS6651 is at home in mainstream consumer applications and can also decode MPEG1 (ISO.IEC 11172-2 ) bitstreams. The CS6651 is available for Xilinx FPGAs and is handcrafted by Amphion for optimal performance while minimizing power consumption and silicon area. Functional Description The CS6651 ASVC is a highly integrated MPEG2 video decoder suitable for a wide range of video applications. The CS6651 accepts the input video elementary stream as aligned bytes from conditional access decryption, transport stream demulti-plexer, or similar source. The core can operate in a default mode on an input stream without the intervention of a host CPU. features can be accessed. All interfacing between the host and the CS6651 is performed through the Host Interface unit. This unit allows read/write access to all the internal control, status and video stream parameter registers contained within the decoder. The Host Interface also provides a simple 32-bit read/write access to the Frame Store SDRAM. Normally, the areas of the SDRAM used for storage of picture data cannot be accessed by the Host Interface; however, a bypass mode allowing direct access is provided for system diagnostic tests, etc. A number of conditions arising from the decoding of the video stream may require the software on the CPU to be alerted. An interrupt controller within the Host Interface unit provides a simple Interrupt Request signal and an interrupt status and mask register. Core I/O Signals The core signal I/O have not been fixed to specific device pins to provide flexibility for interfacing with user logic. Descriptions of all signal I/O are provided in Tabl datasheet. To learn more about the SignOnce IP