description language (HDLs). NoteClick on the part name to see the contents of the Processes for Current Source window.Task 3: Create a Precision RTL Synthesis ProjectHDL Design with Precision RTL Synthesis: CPLD Flow Tutorial7Then it converts the HDL description into small, high-performance design netlists that are optimized for Lattice devices.To start Precision RTL Synthesis:1.In the Project Navigator, choose Tools > Precision Synthesis to open the Precision RTL Synthesis tool.2.Click OK to close the Tip of the Day.3.Choose File > New Project, or click on the New Project icon in the Project pane to open the New Project dialog box, shown in Figure6.4.In the dialog box, do the following:a.In the Project Name box, type syn_mux4to1 .b.In the Project Folder box, make sure the following directory is shown:<install_path>\examples\Tutoprecision_cpld_tutorc.Click OK .Figure 6: New Project Dialog BoxThe Precision RTL Synthesis window looks like that shown in Figure7.Task 4: Add the Verilog features, see the Precision RTL Synthesis Users Manual , Precision RTL Synthesis Style Guide, and Precision Synthesis Reference Manual in the online help.Time to Complete This TutorialHDL Design with Precision RTL Synthesis: CPLD Flow Tutorial2Time to Complete This TutorialThe time to complete this tutorial is about 20 minutes.System RequirementsOne of the following software configurations is required to complete the tutorial:IspLEVER StarterispLEVERAccessing Online HelpYou can find online help information on any tool included in the tutorial at any time by pressing the F1 key.About the Tutorial DesignThe tutorial design consists of a simple 4 to 1 multiplexer, as shown in Figure1:Figure 1: Tutorial DesignThis tutorial first directs you to create an EDIF project in the Project Navigator, then select the target device in which the design will be implemented. It assumes that functional simulation has already been performed. Next, you About the Tutorial Data FlowHDL Design with Precision specifications, or information, or