Description The LP62E16512-I is a low operating current 8,388,608-bit static random access memory organized as 524,288 words by 16 bits and operates on low power voltage from 1.65V to 2.2V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable input is provided for POWER - DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 1.2V. Product Family Power Dissipation Product Family Operating Temperature VCC Range Speed Data Retention (I CCDR, Typ.) Standby (I SB1, Typ.) Operating (I CC2, Typ.) Package Type LP62E1 6512 - 40 C ~ +85 C 1.65V~2.2V 70ns 0.1 m A 0.5 m A 3mA 48 CSP 1. Typical values are measured at VCC = 1.8V, TA = 25 C and not 100% tested. 2. Data retention current VCC = 1.2V. Pin Configurations nn CSP (Chip Size Package) 48 -pin Features n Operating voltage: 1.65V to 2.2V n Access times: 70 ns (max.) n Current: Very low power version: Operat ing: 40mA (max.) Standby: 10 m A (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL- compatible n Common I/O using three-state output n Data retention voltage: 1.2V (min.) n Available in 48-ball CSP (8 10 mm) packages General Description The LP62E16512-I is a low operating current 8,388,608-bit static random access memory organized as 524,288 words by 16 bits and operates on low power voltage from 1.65V to 2.2V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable input is provided for POWER - DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 1.2V. Product Family Po specification is not implied or inte