DESCRIPTIONSCSChip SelectRASCASColumn Address Strobe Command63626160 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44VSSDQ15VSSQ DQ14 DQ13 VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8 NCVSSDQM1NCNCCLKCKE A9 A8A7 A6A5A4A3DQM3VSSNC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27VDDQ DQ26 DQ25 VSSQ DQ24 VSSWEDDDDQQIntegrated Silicon Solution, IncRev. A02/17/09IS42S32800D, IS45S32800DPIN CONFIGURATIONPIN DESCRIPTIONSCSChip SelectRASCASColumn Address Strobe CommandWEDDDDQQIS42S32800D, IS45S32800DIntegrated Silicon Solution, IncRev. A02/17/09PIN FUNCTIONS Symbol TypeFunction (In Detail) A0-A11 CAS CASrefresh mode. asynchronous input. CS Command input is enabled when device remains in the previous state when RAS RAS WE WEDDQ DDQ DD DD is the device internal power supply.SSQ SSQ is the output buffer ground.SS SS is the device internal ground.6Integrated Silicon Solution, IncRev. A02/17/09IS42S32800D, IS45S32800DGENERAL DESCRIPTIONREADand starts a burst read access to an active row. Inputs WRITEA burst write access to an FEATURESpositive clock edgeoperations capabilitycommandOPTIONS Commercial (0oC to +70oooooooOVERVIEWISSIdata transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.8M x 32 256Mb SYNCHRONOUS DRAMFEBRUARY 2009KEY TIMING PARAMETERSParameter-6-7-75EUnit CAS ns CAS CAS CAS CAS ns CASADDRESS TABLEParameter8M x 32Con gurationCom./Ind.A1A2A0 - A11Column AddressesAutoprecharge 2Integrated Silicon Solution, IncRev. A02/17/09IS42S32800D, IS45S32800DDEVICE OVERVIEWDD DDQ and a power-saving, power-down mode. All signals are data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.A self-timed row precharge initiated at the end of the burst enabled. one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, ra Integrated Silicon Solution, Inc Rev. A02/17/0