DESCRIPTION The ADF4108 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. FUNCTIONAL BLOCK DIAGRAM CLKDATALEREFINRFINARFINB24-BIT INPUTREGISTERSDOUTAVDDDVDDCEAGNDDGND14-BITR COUNTERR COUNTERLATCH2214FUNCTIONLATCH FEATURES 8.0 GHz bandwidth 3.2 V to 3.6 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3.3 V systems Programmable, dual-modulus prescaler 8/9, 16/17, 32/33, or 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode Loop filter design possible with ADIsimPLL 4 mm 4 mm, 20-lead chip scale package APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANs Base stations for wireless radio GENERAL DESCRIPTION The ADF4108 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjuncti Specifications subject to change without notic