DESCRIPTION The AD9865 is a mixed-signal front end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 80 MSPS. Its flexible digital interface, power saving modes, and high Tx-to-Rx isolation make it well suited for half- and full-duplex applications. The digital inter-face is extremely flexible allowing simple interfaces to digital back ends that support half- or full-duplex data transfers, thus often allowing the AD9865 to replace discrete ADC and DAC solutions. Power saving modes include the ability to reuce power consumption of individual functional blocks, or to power down unused blocks in half-duplex applications. A serial port interface (SPI) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks from a single crystal or clock source. The Tx signal path consists of a bypassable 2 /4 low-pass interpolation FEATURES Low cost 3.3 V CMOS MxFETM for broadband modems 10-bit D/A converter 2 /4 interpolation filter 200 MSPS DAC update rate Integrated 23 dBm line driver with 19.5 dB gain control 10-bit, 80 MSPS A/D converter 12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz) Third order, programmable low-pass filter Flexible digital data path interface Half- and full-duplex operation Backward-compatible with AD9975 and AD9875 Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs Available in 64-lead chip scale package or bare die APPLICATIONS Powerline networking VDSL and HPNA FUNCTIONAL BLOCK DIAGRAM 10XTALRX-46AD9865100 TO-7.5dB04493-0-0010 TO-12dBREGISTERCONTROLCLKSYN.ADC80MSPS2-4XIOUT_G+IOUT_N+IOUT_N-IOUT_G-CLKOUT_1CLKOUT_2OSCINRX+IAMPTxDACIOUT_P+IOUT_P-2M CLKMULTIPLIER2-POLELPF1-POLELPF0 TO 6dB = 1dB- 6 TO 18dB = 6dB-6 TO 24dB = 6dBSPIAGC[5:0]RXCLKRXE/SYNCADIO[9:4]/Tx[5:0]ADIO[3:0]/Rx[5:0]TXCLKTXEN/SYNCMODEPWRDWN Fiure 1. GENERAL DESCRIPTION Specifications subject to change without no