Description ..3 Specifications ..4 AC Characteristics 5 Timing Characteristics.6 Serial Interface 6 Parallel Interface 9 Absolute Maximum Ratings..11 ESD Caution ..11 Pin Configuration and Function Descriptions.12 Typical Performance Characteristics..15 Terminology .17 Functional Description.18 DAC Architecture General..18 Channel Groups ..18 Transfer Function..18 VBIAS Function ..19 Reference Selection..19 Calibration ..20 Clear Function .20 BUSY and LDAC Functions20 FIFO vs. Non-FIFO Operation.21 BUSY Input Function.21 Power-On Reset Function21 RESET Input Function..21 Increment/Decrement Function.21 Interfaces .22 Parallel Interface .22 Serial Interface .22 Data Decoding 24 Address Decoding 25 Power Supply Decoupling..26 Power-On 26 Typical Application Circuit27 Outline Dimensions 28 Ordering Guide ..28 REVISION HISTORY 4/05 Revision 0: Initial Version AD5378 Rev. 0 | Page 3 of 28 GENERAL DESCRIPTION The AD5378 contains 32 14-bit DACs in one CSPBGA package. The AD FEATURES 32-channel DAC in 13 mm 13 mm 108-lead CSPBGA Guaranteed monotonic to 14 bits Buffered voltage outputs Output voltage span of 3.5 V VREF(+) Maximum output voltage span of 17.5 V System calibration function allowing user-programmable offset and gain Pseudo differential outputs relative to REFGND Clear function to user-defined REFGND (CLR pin) Simultaneous update of DAC outputs (LDAC pin) DAC increment/decrement mode Channel grouping and addressing features Interface options Parallel interface DSP/microcontroller-compatible 3-wire serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels SDO daisy-chaining option Power-on reset Digital reset (RESET pin and soft reset function) APPLICATIONS Level setting in automatic test equipment (ATE) Variable optical attenuators (VOAs) Optical switches Industrial control systems FUNCTIONAL BLOCK DIAGRAM VCCVDDVSSAGNDRESETPOWER-ONRESETDGNDLDACVBIASVREF1(+)VREF1(-)REFGND A1VBIASDAC 0-1DAC0-1DACREG2DACREG5DACREG6-7INPUTREG0-1INPUTREG2INPUTR Specifications subject to change without notic