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1/10I - INTRODUCTIONThis is the Errata Sheet of th
specification has been added:Notet28 (Address hold after RD, WR, WRL) is inside thespecification limit: t28min>0ns.V - AC/DC PROBLEM HISTORYThe following AC/DC problems have been fixedbetween the ST10C167-A0 and ST10R167-B0revisions.NoteThe READY pin does not have a pullup. This will be thecase for all ST10 products with Programmable READYPolarity.independent of whether or not the respective pins are usedfor CSx function after reset.VI - MARKING HISTORYVII - REVISION HISTORYThis is the first release of this document.ADC.7Channel injection coincident with start of Standard ConversionFixed in step B0ADC.10Start of Standard Conversion at end of Injected ConversionFixed in step B0Kgpt_BR01Bit 10 of T5CON always read as 0Fixed in step B0Kan_BR01CAN is only functional for maximum baudrateFixed in step B0Kan_BR02CAN internal circuitryFixed in step B0Table 6 : Re-specified AC Characteristics, Demux bus modesParameterSymbolMax. CPU Clock= 25 MHzVariable CPU Clock1/2TCL = 1 to 25MHzUnitmin.max.m 1/10I - INTRODUCTIONThis is the Errata Sheet of th Datasheet;VN750SM
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Relevant Keywords:
B0t39CS, ST10, CPU.17, ST10R167-B0The, B0t16ALE, SHRR0, C166, ST10R167-A0, B0Kan_BR02CAN, RTX166, XRAM.TRAP_B.1, BUGSST_ADC.1, ST10R167, B0Kan_BR01CAN, MDLF0F00F0FhF0F0hFFFF, WRHt28hCC-5, B0t46/t47RdCS, ST10C167-A0, 0ChSUBR0,01, JNBADCON.5, T5CON
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