Description The core is made up of several functional blocks, as shown in the block diagram and described below. R8051XC-CPU This unit contains instruction execution FSM along with dedicated registers, such as Program Counter, Stack Pointer and Data Pointer(s). The Arithmetic-Logic Unit is also implemented in this module, together with the following registers: Accumulator, B and Program Status Word. Moreover, the CPU module provides and services interfaces to program and external data memory, on-chip data memory, and Special Function Registers. Feature summary of the R8051XC-CPU: 8-bit Control Unit reducing instruction cycle time up to 12 times 8-bit Arithmetic-Logic Unit executing arithmetic and logi-cal operations, Boolean manipulations, multiplication and division Internal Data Memory interface addressing up to 256 B of Data Memory Space Special Function Registers (SFR) interface - servicing from 59 to 118 SFRs, depending on the peripheral con-figuration External memory interface al features an HDLC serial interface. The HDLC portion of the solution provides needed serialization and de-serialization. It also supports auto-matic response generation for window size equal to 1. HDLC Connectivity Platform retains features of the R8051XC configurable 8-bit mi-crocontroller. It provides interrupts, interfaces for serial communication, timer system with compare-capture-reload resources, I/O ports, a power management unit, a multipli-cation-division unit, DMA controller, watchdog timer, and a real time clock. The extensive set of peripherals included can be easily modified to meet the requiremea specific application. The HDLC Connectivity Platform is a design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no in-ternal tri-states and with a synchronous reset; therefore scan insertion is straightforward. Block Diagram -bit controller Fast single clock per cycle CPU Flexible interfaces to program and data specifications and a system integration guide