DESCRIPTION8 Package8-Lead PDIP (Narrow .300 Inch)(Reference LTC DWG # 05-08-1510)S8 Package8-Lead Plastic Small Outline (Narrow .150 Inch)(Reference LTC DWG # 05-08-1610)N8 1002 .065(1.651)TYP.045 .065(1.143 1.651).130 .005(3.302 0.127).020(0.508)MIN.018 .003(0.457 0.076).120(3.048)MIN(0.203 0.381)(7.620 8.255).325+.035 .015+0.889 0.3818.255 () 1234876 5 .255 .015*(6.477 0.381) .400*(10.160)MAXNOTE:1. DIMENSIONS AREINCHESMILLIMETERS*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm).100(2.54)BSC.016 .050(0.406 1.270).010 .020(0.254 0.508) 45 0 8 TYP.008 .010(0.203 0.254)SO8 0502.053 .069(1.346 1.752).014 .019(0.355 0.483)TYP.004 .010(0.101 0.254).050(1.270)BSC1N234 N/2.150 .157(3.810 3.988)NOTE 38765.189 .197(4.801 5.004)NOTE 3.228 .244(5.791 6.197).245MINN123N/2 .160 .005RECOMMENDED SOLDER PAD LAYOUT.045 .005 .050 BSC.030 .005 TYPINCHES(MILLIMETERS) NOTE:1. DIMENSIONS IN 2. DRAWING NOT TO SCALE3. THESE DIMENSIONS features ultralow power consumption without sacrificingESD and latch-up immunity.The LTC1481 uses a proprietary driver output stage,which allows a common mode range that extends beyondthe power supplies while virtually eliminating latch-up andproviding excellent ESD protection. Figure 9 shows theLTC1481 output stage while Figure 10 shows a conven-tional CMOS output stage.When the conventional CMOS output stage of Figure 10enters a high impedance state, both the P-channel (P1)and the N-channel (N1) are turned off. If the output is thendriven above VCC or below ground, the P+/N-well diode(D1) or the N+/P-substrate diode (D2) respectively willturn on and clamp the output to the supply. Thus, theoutput stage is no longer in a high impedance state and isnot able to meet the RS485 common mode range require-ment. In addition, the large amount of current flowingthrough either diode will induce the well-known CMOSlatch-up condition, which could destroy the device.The LTC1481 output stage of Fig specifications which apply over the full opera