descriptions are shown in Table1 .Table 1:FCB V20 I/O Signals Port NameMSB:LSBI/ODescriptionFCB_CLKIFCB ClockSYS_RstIExternal System ResetFCB_RstOFCB ResetM_DECUDIVALIDIConnects to APUFCMDECUDIVALID of PPC440M_ENDIANIConnects to APUFCMENDIAN of PPC440M_FLUSHIConnects to APUFCMFLUSH of PPC440 APUFCMINSTRUCTION of PPC440M_INSTRVALIDIConnects to APUFCMINSTRVALID of PPC440M_LOADDVALIDIConnects to APUFCMLOADDVALID of PPC440M_OPERANDVALIDIConnects to APUFCMOPERANDVALID of PPC440M_WRITEBACKOKIConnects to APUFCMWRITEBACKOK of PPC440M_DECFPUOPIConnects to APUFCMDECFPUOP of PPC440M_DECLOAD IConnects to APUFCMDECLOAD of PPC440M_DECSTORE IConnects to APUFCMDECSTORE of PPC440Connects to APUFCMDECLDSTXFERSIZE of PPC440M_DECNONAUTON IConnects to APUFCMDECNONAUTON of PPC440M_NEXTINSTRREADY IConnects to APUFCMNEXTINSTRREADY of PPC440M_MSRFE0 IConnects to APUFCMMSRFE0 of PPC440M_MSRFE1 IConnects to APUFCMMSRFE1 of PPC440Multiplexed from Sl_CR as selected by Sl_RESULTVALIDFCB_DONEOLogical OR of DONE sign FeaturesSingle master supportMultiple slave supportSlave access selection based on instruction codeNo arbitration between slaves(FCM) interface of the APU controllerFabric Coprocessor Bus for theVirtex-5 FPGA EmbeddedProcessor Block (v1.00a)DS725 April 24, 2008ProductSpecificationLogiCORE IP FactsCore SpecificsSupported Device Family See EDK Supported Device Families .Resources UsedMinMaxSlicesN/AN/ALUTs0214(1)1.Assuming three full feature FCB slaves. The actual size dependssignals that they use.FFs00Block RAMs00Special FeaturesAdd if applicableProvided with CoreDocumentationProduct SpecificationDesign File FormatsVHDLConstraints FileN/AVerificationN/AInstantiation TemplateN/AAdditional ItemsNoneDesign Tool RequirementsXilinx Implementation Tools See Tools for requirements.VerificationSimulationSynthesisSupportProvided by Xilinx, Inc.Fabric Coprocessor Bus for the Virtex-5 FPGA Embedded Processor Block (v1.00a)2www.xilinx.comDS725 April 24, 2008ProductSpecificationI/O SignalsThe FCB V2 Specification -20082009 Xilinx, Inc. XILINX, t