DescriptionsSignal Signal DirectionWidthDescriptionClocks and Data IOclkInput1System clocksclrInput1System sync reset (active high)ceInput1Not used in this version of the core. The user should drive this input to 1. host_error_intOutput1Error interrupt flag outputvideo_in_clkInput1Input pixel-rate clockactive_video_inInput1Write-enable to input data FIFOvideo_inInput16YC data input:(7:0): Luma(15:8): Chromaline_requestOutput1Input data FIFO may accept another input line chroma_inInput1Chroma input-line validation. 4:2:2 operation: set to 1 permanently4:2:0 operation: set to 1 for active chroma lines only.vblank_inInput1Vertical synchronization pulse must be high during blanking periodhblank_inInput1Horizontal synchronization pulse must be high during blanking periodvideo_outOutput16YC data output(7:0): Luma(15:8): Chromavideo_out_clkInput1Output pixel-rate clockvideo_out_fullInput1Full flag input from next blockvideo_out_weOutput1Write-enable to outputchroma_outOutput14:2:0 chroma outp FeaturesSupports Virtex-5 (all speed grades) and Spartan-3A DSP (-5 speed grade only) devices.Independently programmable scaling factor for horizontal and vertical sizeSupport for YUV4:2:2 or YUV4:2:0 Support for 2-12 taps in both horizontal and vertical directionsases for each coefficient set (2-16 inclusive, or 32 or 64)Internal storage for up to 16 coefficient setsNegative start phase support Programmable subject and target area sizeUser-loadable 16-bit coefficients. Highly scalable resolution support from 176x144 to 1920x1080p; supported standard HD formats are 1080i/60, 720P/60, 1080P/30 Support for real-time streaming or frame buffer processing ApplicationsPost-processing block for image scalingMedical EndoscopeVideo SurveillanceConsumer DisplaysVideo ConferencingMachine VisionGeneral IntroductionVideo scaling is the process of converting an input colorimage of dimensions Xin pixels by Yin lines to an outputcolor image of dimensions Xout pixels by Yout lines. Video scaling is a f Specification 2009 Xilinx, Inc. Xilinx, Inc. X