Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.1Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.2Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 134.3Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.4Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 144.5Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.6Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.7Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features Core 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipelineExtended instruction setMemories Program memory: 8 Kbytes Flash; data retention 20 years at 55 C after 10 kcyclesData memory: 640 bytes true data EEPROM; endurance 300 kcyclesRAM: 1 KbytesClock, reset and supply management2.95 to 5.5 V operating voltageFlexible clock control, 4 master clock sources:Low power crystal resonator oscillator External clock inputInternal, user-trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitorPower management:Low power modes (wait, active-halt, halt)Switch-off peripheral clocks individuallyPermanently active, low consumption power-on and power-down resetInterrupt managementNested interrupt controller with 32 interruptsUp to 27 external interrupts on 6 vectorsTimers Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization16-bit general purpose timer, with 3 CAPCOM chan June 200915441 Rev 31/951STM8S103F3 STM8S103F2