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ADF4001 200 MHz Clock Generator PLL Data Sheet (REV. A)


DESCRIPTIONThe ADF4001 clock generator can be used to implement clocksources for PLLs that require very low noise, stable referencesignals. It consists of a low noise digital PFD (phase frequencydetector), a precision charge pump, a programmable referencedivider, and a programmable 13-bit N counter. In addition, the14-bit reference counter (R counter) allows selectable REFINfrequencies at the PFD input. A complete PLL (phase-lockedloop) can be implemented if the synthesizer is used with an exter-nal loop filter and VCO (voltage controlled oscillator) orVCXO (voltage controlled crystal oscillator). The N minimumvalue of 1 allows flexibility in clock generation.REV. A2ADF4001SPECIFICATIONS 1 (AVDD = DVDD = 3 V 10%, 5 V 10%; AVDD V P 6.0 V ; AGND = DGND =CPGND = 0 V; RSET = 4.7 k; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .)ParameterB VersionUnitTest Conditions/CommentsRF CHARACTERISTICS (3 V) See Figure 3 for Input CircuitRF Input Frequency5/165MHz min/maxRF Input Sen FEATURES200 MHz Bandwidth2.7 V to 5.5 V Power SupplySeparate Charge Pump Supply (VP) Allows ExtendedTuning Voltage in 5 V SystemsProgrammable Charge Pump Currents3-Wire Serial InterfaceHardware and Software Power-Down ModeAnalog and Digital Lock DetectHardware Compatible to the ADF4110/ADF4111/ADF4112/ADF4113Typical Operating Current 4.5 mAUltralow Phase Noise16-Lead TSSOP20-Lead LFCSPAPPLICATIONSClock GenerationLow Frequency PLLsLow Jitter Clock SourceClock SmoothingFrequency TranslationSONET, ATM, ADM, DSLAM, SDMGENERAL DESCRIPTIONThe ADF4001 clock generator can be used to implement clocksources for PLLs that require very low noise, stable referencesignals. It consists of a low noise digital PFD (phase frequencydetector), a precision charge pump, a programmable referencedivider, and a programmable 13-bit N counter. In addition, the14-bit reference counter (R counter) allows selectable REFINfrequencies at the PFD input. A complete PLL (phase-lockedloop) can be implemented if the synth SPECIFICATIONS 1 (AVDD = DVDD = 3 V 10%, 5 V 1

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Relevant Keywords: 
ABP1, EVAL-ADF4001EB1, SETTING2, CHARACTERISTICSADF4001, LELEDB0, CPI6CPI5CP14ICP, OPERATION101ASYNCHRONOUS, DB22DB23, RESERVED13-BIT, ABP2T1, HP8562E, VDD/2, CP-20ADF4001BCP-REEL740, MHz00AMPLITUDE, DB19DB2, POWER-DOWN111SYNCHRONOUS, AADF4001, ESERVED13-BIT, SETTING1, BITS.F4, LE13, CPI3CPI4, N2N3, DB21R12R11R10DB23, RATIO000, ABP2ABP1ANTIBACKLASH, GND3, VCXO.76, CP-20ADF4001BCP-REEL40, MHz.5The, DB1(CONTROL, POWER-DOWN, A2ADF4001SPECIFICATIONS, DVDD16, SET.1FIVE, AGNDAVDDBIASGENERATOR2k, II.ADF4001, WIDTH14-BIT, CPI1CPI2CPI5CPI6TC4PD2F2, N13N12N11N3N2N1N, DB21R12R11R10, R8R9, ABP2, F4F5, THAN15ns, COUNTERNCNOSW1SW3SW2NC100k, M235.So, DATA12, PINPD2PD1MODE0, 2TC3TC2TC1DB23, DIAGRAMRFINARFINB13-BITN, RSET18, ADF4001TIMING, I.C2, VP17, CPI1CPI2CPI5CPI6TC4PD2, N12N13N7G1, DB21, R14R13R12.R3R2R1DIVIDE, ABP1T2LDPR13R6, F2CONT, T2LDPR13R6CONT, COUNTERDB21, M1M2M3, CPTHREE-STATE, PFD13-BIT, 2TC3TC2TC1, DGND15, RFINBRFINA2k, ADF4001, Hz40100PHASE, VIEWADF4001CPGND, CP11, N10N11N6N5N4, DB20(MSB), POWER-DOWN1X0NORMAL
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