specifications (all timing specifications in are ns) from the DDR2 device data sheet: tRAS tRP tWTR tRCD tRTP Expert Code Generator for ADSP-2146x SHARC Processors (EE-322) Page 5 of 17 tRRD tFAW tWR tREFI tRFC tCK max (minimum DDR2 clock frequency supported by the device) Banks (number of banks) CAW (column address width) RAW (row address width) DDCL (CAS latency) DDAL (additive latency) 2. In ODT (Rtt), Select Disabled to disable on-die termination, or select the corresponding value for Rtt. 3. In DQS Enable, select Enabled or Disabled according to the systems requirements. 4. In Optimize Reads and Read Modifier, select Yes if predictive reads are needed, and select the corresponding modifier value. 5. In Include Subroutines to, select options to generate separate subroutines for entering and exiting Self Refresh and Power Down modes. Corresponding options should be checked to generate these subroutines along with the PLL_DDR2_AMI subroutine. 6. Under Select Module, select the DDR2 c Expert Code Generator for ADSP-2146x SHARC Proces Application Notes, EE-Notes, ADSP-2146x, SHARC, DDR2, PLL, AMI, FFT, IIR, FIR, C, ASM