Low voltage 0.5 max dual SPDT switch, single enable with break before make feature
DESCRIPTIONANALOG S.P.D.T. (Single Pole Dual Throw)SWITCH or DUAL 2:1 Multiplexer/DemultiplexerBus Switch fabricated in silicon gate C2MOStechnology. It is designed to operate from 1.4V to4.3V, making this device ideal for portableapplications.It offers very low ON-Resistance (<0.5) atV CC=3.0V. The IN input is provided to control theswitches. The switches nS1 are ON (they areconnected to common Ports Dn) when the IN inputis held high and OFF (high impedance state existsbetween the two ports) when IN is held low; theswitches nS2 are ON (they are connected tocommon Ports Dn) when the IN input is held lowand OFF (high impedance state exists betweenthe two ports) when IN is held high. Additional keyfeatures are fast switching speed, Break BeforeMake Delay Time and Ultra Low PowerConsumption. All inputs and outputs are equippedwith protection circuits against static discharge,giving them ESD immunity and transient excessvoltage. Its available in the commercialtemperature range Flip-chip pa features are fast switching speed, Break BeforeMake Delay Time and Ultra Low PowerConsumption. All inputs and outputs are equippedwith protection circuits against static discharge,giving them ESD immunity and transient excessvoltage. Its available in the commercialtemperature range Flip-chip package with EpoxyProtection.STG3685LOW VOLTAGE 0.5 MAX DUAL SPDT SWITCH,SINGLE ENABLE WITH BREAK BEFORE MAKE FEATUREThis is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Flip-ChipFigure 1: Pin Connection (Top Through View) And Schematic CircuitTable 1: Order Codes PACKAGET & R Flip-Chip9STG3685BJRFlip-ChipPRELIMINARY DATARev. 2STG36852/10Figure 2: Input Equivalent Circuit Table 2: Pin Description Table 3: Truth Table (*) High ImpedanceTable 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.( Specifications Note 1: Flatness is defi
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