description for STM32F10xxx low-density devices Only the limitations described below have an impact, even though minor, on the implementation of STM32F10xxx low-density devices.All the other limitations described in the ARM errata notice (and summarized in Table3 above) have no impact and are not related to the implementation of STM32F10xxx low-density devices (Cortex-M3 r1p1-01rel0).Table 3.Cortex-M3 core limitations and impact on microcontroller behaviorARM IDARM category ARM summary of errataImpact on low-density STM32F10xxx devices602117Cat 2LDRD with base in list may result in incorrect base register when interrupted or faultedMinor563915Cat 2Event register is not set by interrupts and debugMinor531064implSWJ-DP missing POR reset syncNo 511864Cat 3Cortex-M3 may fetch instructions using incorrect privilege on return from an exceptionNo 532314Cat 3DWT CPI counter increments during sleepNo538714Cat 3Cortex-M3 TPIU clock domain crossingNo548721Cat 3Internal write buffer could be activ feature an ARM 32-bit Cortex-M3 core, for which an errata notice is also available (see Section1 for details).The full list of root part numbers is shown in Table2 .The products are identifiable as shown in Table1 :by the Revision code marked below the Sales Type on the device package Table 1.Device Identification(1)1.The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the STM32F10xxx reference manual for details on how to find the revision code).Sales typeRevision code(2) marked on device2.Refer to for details on how to identify the Revision code on the different packages.STM32F103xxxxA (3)3.All MCUs with 16 KB of Flash memory are concerned (they all have the letter A in their commercial code). Among devices with 32 KB of Flash memory, only those identified by the letter A in their commercial code are concerned. For devices with 32 KB of Flash memory that do not have the letter A, refer to the medium-density errata sheet.A (3) ASTM32F102xxxxA (3)ATa datasheet).WorkaroundTo have a fully stabilize