DescriptionThe STCCP27A receiver converts the subLVDS clock/datastream (up to 416 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/ LVTTL. The device recognizes the CCP 32bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to Output LVTTL clock (up to 52 MHz) is transmitted in parallel with data. Input and Output data are rising edge strobe. This chipset is an ideal means to link mobile camera modules to baseband processors. In order to minimize static current consumption, it is possible to shut down the device when the interface is not being used by a power-down (EN) pin that reduces to 10A the Maximum Current Consumption making this device ideal for portable applications like Mobile Phone, Portable Battery Equipment. Two dedicated I2C lines are provided to translate bidirectional controls from camera and C devices. The STCCP27A is offered in a TFBGA outputs are equipped with protection circuits against static discharge, giving Feature summaryV ID = 100mV with RT = 100 , C L =10pFHigh signaling rate:f IN = 416MHz max (D+,D-, CLK+, CLK-)f OUT = 52MHz max (D1-D8, CLK)Very high speed:t pLH ~t pHL=3.5ns (typ) at VDD=2.8V; VL=1.8V Operating voltage range:V DD(OPR) = 2.65V to 3.6VVL(OPR) =1.65V to 1.95VSymmetrical output impedance(D1-D8, H-SYNC, V-SYNC, CLK):II OHI=I OL=8mA (min) at VDD=2.65V;V L=1.8V Low power dissipation(Disabled: EN=Gnd):ISOFF = IDD + IL = 10A (max)CMOS logic input threshold (EN, SYNC_SEL):V IL = 0.3xVDD ; V DD =2.65V to 3.6VV IH = 0.7xVDD; VDD =2.65V to 3.6VBidirectional level translator line(I/OV DD, I/OV L) for I2C communications:400kHz max frequencyII OHI= 20A (min.) at VDD=2.8V;V L=1.8V I OL = 1 mA (min.) at VDD=2.8V;V L=1.8V 3.6V Tolerant on inputs (EN, SYNC_SEL)Leadfree TFBGA package(RoHS restriction of hazardous substances).DescriptionThe STCCP27A receiver converts the subLVDS clock/datastream (up to 416 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/ LVTTL. The device reco specifications are available at: www.st.com. P