DESCRIPTIONFig. 1 depicts the simplified schematic showing the converter power stage. It is worth notiicing that VddPower identifies the power source of the VRM; the voltage supplying the control circuitry, referred to asVdd Logic and whose value is 6.1V, is obtained through a series regulator implemented with discretecomponents. Figure 1: Simplified SchematicAt start-up, when power is supplied to the converter, Vdd Power increases, as fig.2 shows, due to thecharging of the input capacitors. During this phase, i.e. until the supply voltage reaches the under voltagelockout, the control circuitry should keep low both the high side gate and the low side one; after that thehigh side device should be allowed to start switching with 180 phase shift with respect to the low sideone. The Vdd Power rise should not have any consequence on the gate voltage of the high-side switch.On the contrary in the examined situation it happens that the Vdd Power rise greatly affects themeasured voltage of the specifications reported in the data-sheet regarding the undervoltage lockouts, during thestart-up phase both the driver and the controller should remain OFF. The power switches should remainOFF too. In the examined case this is not true: the control part of the converter seems not workingcorrectly thus leaving the source pins of the high-side switch connected by impedance not low enough oreven floating.As a consequence there is a time interval (200 s) when the high-side gate-source voltage is above thethreshold voltage. So the high side MOSFET realizes a low impedance path (see fig. 1) between the VddPower bus (voltage is rising) from one side and the output capacitors (discharged) and the P from theother one. Series inductance L1 is unable to limit current so this can be a reasonable source of stressAN1872 - APPLICATION NOTE3/5and failure for the MOSFET and the P.Figure 2: Waveform during TestFigure 3: Typical Power MOSFET Capacitance Ratio as a Function of Drain-To-Source VoltageAN18 AN1872 - APPLICATION NOTE2/53. PROBLEMS DESCRI