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LIS331DLM: 2 g /4 g /8 g digital output high performance ultra low-power 3-axis accelerometer


DescriptionMinT0Data rate1/ODRT1Reading periodT0-T2T2New data generation (typ)616 sTable 4.Data signal on INT 1 and INT 2 padsI1(2)_CFG1I1(2)_CFG0INT 1(2) pin00Interrupt 1 (2) source01Interrupt 1 source OR Interrupt 2 source10DataReady11Boot running Startup sequenceAN298910/28 Doc ID 15761 Rev 1Figure 2.Interrupt and DataReady signal generation block diagramIn particular, the DataReady (DR) signal rises to 1 when a new set of acceleration data has been generated and is available for reading. The signal is reset after all the enabled channels are read through the serial interface.Figure 3.DataReady signal2.4 Understanding acceleration dataThe measured acceleration data are sent into the OUTX, OUTY, OUTZ registers.Acceleration data for the X (Y, Z) channel is expressed as a 2s complement number.2.4.1 Data alignmentAcceleration data are represented as 8-bit numbers, twos complement and are right justified.2.4.2 Example of acceleration dataTable5 provides a few basic examples of the data t features ultra low-power operational modes that allow advanced power saving and smart sleep to wake functions.The LIS331DLM has dynamically user-selectable full scales of 2 g /4 g /8 g and is capable of measuring acceleration with output data rates from 0.5 Hz to 400 Hz.The self-test capability allows the user to check the functioning of the sensor in the final application.The device can be configured to generate interrupt signals in response to inertial wakeup/free-fall events or based on the position of the device itself.The thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS331DLM is available in a small, thin plastic land grid array (LGA) package and is guaranteed to operate over an wide temperature range of -40 C to +85 C.www.st.com Contents AN29892/28 Doc ID 15761 Rev 1Contents1Register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Startup sequence . . . . . . . . . . . . . . . datasheet of the device, the power-mode (PM) a

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CTRL_REG12, INT2_THS9, DR10, Hz400, INT1_THS7, CTRL_REG34, STATUS_REG(3), Hz1015204080400, I2C/SPI, CTRL_REG1, INT2_DUR10, CTR_REG5, Hz37, INT1_DUR8, CTRL_REG3, ODR50, Hz100, I1(2)_CFGx, AN29892/28, INT2_CFG13, CTR_REG1, Hz292, INT1_CFG12, CTRL_REG23, LIS331DLM, Hz10, Hz74, 23AN2989, INT2_CFG, CTRL_REG5, STATUS_REG2if, Hz10400, INT1_CFG, CTRL_REG13, LIS331DLH, Hz01100, Hz50, 0x01, INT2, CTRL_REG45, STATUS_REG(7), Hz1020306099100, INT1

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I2C/SPI Xref I2C/SPI 示意圖 I2C/SPI Inventory I2C/SPI Distribution
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Hz01100 數據 Hz01100 Design Idea Hz01100 Distributor Hz01100 MOQ
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