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Using the Virtex Delay-Locked Loop


The Virtex FPGA series offers up to eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits providing zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits, which improve and simplify system-level design.

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XAPP138, XAPP132.zip, XAPP132, Virtex Series
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Related Datasheets: 
AD8389 Triple, 6-Channel LCD Timing Delay-Locked Loop Data Sheet (REV. 0)
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Other Descriptions

XAPP132.zip Esquema XAPP132.zip Component XAPP132.zip Operating Parameter XAPP132.zip Mechanical Outline
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