2GB DDR2 SDRAM SO-DIMM EBE21UE8ACUA(256M words - 64 bits, 2 Ranks)
Double-data-rate architecture; two data transfers per clock cycle, The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture , Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver, DQS is edge-aligned with data for READs; centeraligned with data for WRITEs, Differential clock inputs (CK and /CK)
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EBE21UE8ACUA-8G-E, EBE21UE8ACUA-8E-E, EBE21UE8ACUA-6E-E, EBE21UE8ACUA, E1217E10
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