Double-data-rate architecture; two data transfers per clock cycle , The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture, Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver, Data inputs, outputs, and DM are synchronized with DQS, DQS is edge-aligned with data for READs; centeraligned with data for WRITEs, Differential clock inputs (CK and /CK) , DLL aligns DQ and DQS transitions with CK transitions, Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS, Data mask (DM) for write data