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12 x 12-bit Parallel Multiplier


The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology.The LMU112 is pin and functionally compatible with Fairchilds's MPY112K. The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A and CLK B). Two's complement or unsigned magnitude operands are accommo- dated via the operand control bit (TC)

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LMU112PC25, LMU112JC50, LMU112JC25, LMU112, LMU112PC50, LMU112
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4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER

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